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datasheet 3.3v 1:12 lvcmos pll clock generator MPC9772 nrnd MPC9772 revision 7 january 8, 2013 1 ?2013 integrated device technology, inc. the MPC9772 is a 3.3 v compatible, 1: 12 pll based clock generator targeted for high performance low-skew clock distribution in mid-range to high-performance networking, computing and telecom applications. with output frequencies up to 240 mhz and output skews less than 250 ps the device meets the needs of the most demanding clock applications. features ? 1:12 pll based low-voltage clock generator ? 3.3 v power supply ? internal power-on reset ? generates cock signals up to 240 mhz ? maximum output skew of 250 ps ? on-chip crystal oscillator clock reference ? two lvcmos pll reference clock inputs ? external pll feedback supports zero-delay capability ? various feedback and output dividers (see applications information section) ? supports up to three individual generated output clock frequencies ? synchronous output clock stop circu itry for each individual output for power down support ? drives up to 24 clock lines ? ambient temperature range 0 ? c to +70 ? c ? pin and function compatible to the mpc972 ? 52-lead pb-free package ? nrnd ? not recommend for new designs use replacement part ics87972dyi-147 functional description the MPC9772 utilizes pll technology to fr equency lock its outputs onto an input re ference clock. normal operation of the MPC9772 requires the connection of the pll feedback output qfb to feedback input fb _in to close the pll feedback path. the reference clock frequency and the divider for the feedback path determine the vco frequency. both must be selected to match the vco frequency range. the MPC9772 feat ures an extensive level of frequency pr ogrammability between the 12 outputs as well as the output to input relationships, fo r instance 1:1, 2:1, 3:1, 3:2, 4:1, 4:3, 5:1, 5:2, 5:3, 5:4, 5:6, 6:1, 8:1, and 8: 3. the qsync output will indicate when the coincident rising edges of the above relationships will occur. the selectability of the feedback frequency is independent of the output frequencies. this allows for very flex ible programming of the input reference versus output frequency relationship. the output frequencies can be either odd or even multiples of the input reference. in add i- tion the output frequency can be less than t he input frequency for applications where a frequency needs to be reduced by a non- binary factor. the MPC9772 also supports the 180 ? phase shift of one of its output banks with respect to the other output banks. the qsync outputs reflects the phase relationship between the qa and qc outputs and can be used for the generation of sys- tem baseline timing signals. the ref_sel pin selects the internal crystal oscillator or the lvcmos compatible inputs as the reference clock signal. two alternative lvcmos compatible clock inputs are provided for clock redundancy support. the pll_en control selects the pll bypass configuration for test and diagnosis. in this configuration, the selected input reference clock is routed directly to th e output dividers bypassing the pll. the pll bypass is fully static and the minimum clock frequency spec ification and all other pll char - acteristics do not apply. the outputs can be individually disabled (stopped in logic low st ate) by programming the serial clock_stop interface of the MPC9772. the MPC9772 has an internal power-on reset. the MPC9772 is fully 3.3 v compatible and requires no exter nal loop filter components. all inputs (except xtal) accept lvcmos signals while the outputs provide lvcmos compat ible levels with the capability to drive terminated 50 ? transmission lines. for series terminated transmission lines, each of the mpc9 772 outputs can drive one or two traces giving the devices an effective fanout of 1:24. the dev ice is pin and function compatible to the mpc972 and is packaged in a 52-lead lqfp package. 3.3 v 1:12 lvcmos pll clock generator ae suffix 52-lead lqfp package pb-free package case 848d-03 MPC9772 nrnd ? not recommend for new designs
MPC9772 revision 7 january 8, 2013 2 ?2013 integrated device technology, inc. MPC9772 data sheet 3.3v 1:12 lvcmos pll clock generator figure 1. logic diagram figure 2. MPC9772 52-lead package pinout (top view) pll ? 4, ? 6, ? 8, ? 12 0 1 1 0 1 0 1 0 qfb qsync 12 3 2 2 2 all input resistors have a value of 25k ? 1 0 xtal_in xtal_out cclk0 cclk1 fsel_a[0:1] fsel_b[0:1] fsel_c[0:1] inv_clk qa0 qa1 qa2 qa3 qb0 qb1 qb2 qb3 qc0 qc1 bank a bank b bank c clock stop vco ref fb sync pulse ? 4, ? 6, ? 8, ? 10 ? 12, ? 16, ? 20 ? 2, ? 4, ? 6, ? 8 ? 4, ? 6, ? 8, ? 10 qc2 qc3 fsel_fb[0:2] stop_data stop_clk mr /oe cclk_sel ref_sel fb_in vco_sel pll_en v cc clk stop clk stop clk stop clk stop clk stop xtal v cc v cc v cc ? 2 ? 1 power-on reset fsel_b1 fsel_b0 fsel_a1 fsel_a0 qa3 v cc qa2 gnd qa1 vcc qa0 gnd vco_sel fsel_fb1 qsync gnd qc0 v cc qc1 fsel_c0 fsel_c1 qc2 v cc qc3 gnd inv_clk gnd qb0 v cc qb1 gnd qb2 v cc qb3 fb_in gnd qfb v cc fsel_fb0 gnd mr/oe stop_clk stop_data fsel_fb2 pll_en ref_sel cclk_sel cclk0 cclk1 xtal_in xtal_out vc c_pll 40 41 42 43 44 45 46 47 48 49 50 51 52 25 24 23 22 21 20 19 18 17 16 15 14 1 2 3 4 5 6 7 8 9 10111213 39 38 37 36 35 34 33 32 31 30 29 28 27 26 MPC9772
MPC9772 revision 7 january 8, 2013 3 ?2013 integrated device technology, inc. MPC9772 data sheet 3.3v 1:12 lvcmos pll clock generator table 1. pin configuration pin i/o type function cclk0 input lvcmos pll reference clock cclk1 input lvcmos alternative pll reference clock xtal_in, xtal_out analog crystal oscillator interface fb_in input lvcmos pll feedback signal input, connect to an qfb cclk_sel input lvcmos lvcmos clock reference select ref_sel input lvcmos lvcmos/pecl reference clock select vco_sel input lvcmos vco operating frequency select pll_en input lvcmos pll enable/pll bypass mode select mr /oe input lvcmos output enable/disable (high-impedan ce tristate) and device reset fsel_a[0:1] input lvcmos frequency divider select for bank a outputs fsel_b[0:1] input lvcmos frequency divider select for bank b outputs fsel_c[0:1] input lvcmos frequency divider select for bank c outputs fsel_fb[0:2] input lvcmos frequency divider select for the qfb output inv_clk input lvcmos clock phase selection for outputs qc2 and qc3 stop_clk input lvcmos clock input for clock stop circuitry stop_data input lvcmos configuration data input for clock stop circuitry qa[0-3] output lvcmos clock outputs (bank a) qb[0-3] output lvcmos clock outputs (bank b) qc[0-3] output lvcmos clock outputs (bank c) qfb output lvcmos pll feedback output. connect to fb_in. qsync output lvcmos synchronization pulse output gnd supply ground negative power supply v cc_pll supply v cc pll positive power supply (analog power supply) . it is recommended to use an external rc filter for the analog power supply pin v cc_pll . please see applications section for details. v cc supply v cc positive power supply for i/o and core. all v cc pins must be connecte d to the positive power supply for correct operation
MPC9772 revision 7 january 8, 2013 4 ?2013 integrated device technology, inc. MPC9772 data sheet 3.3v 1:12 lvcmos pll clock generator table 2. function table (configuration controls) control default 0 1 ref_sel 1 selects cclkx as the pll reference clock selects the crystal oscillator as the pll reference clock cclk_sel 1 selects cclk0 selects cclk1 vco_sel 1 selects vco ? 2. the vco frequency is scaled by a factor of 2 (low vco frequency range). selects vco ? 1. (high vco frequency range) pll_en 1 test mode with the pll bypassed. the reference clock is substituted for the internal vco output. MPC9772 is fully static and no minimum frequency limit applies. all pll related ac characteristics are not applicable. normal operation mode with pll enabled. inv_clk 1 qc2 and qc3 are in phase with qc0 and qc1 qc2 and qc3 are inverted (180 ? phase shift) with respect to qc0 and qc1 mr /oe 1 outputs disabled (high-impedance st ate) and device is reset. during reset/output disable the pll feedback loop is open and the internal vco is tied to its lowest frequency. the MPC9772 requires reset after any loss of pll lock. loss of pll lock may occur when the external feedback path is interrupted. the length of the reset pulse should be greater than one reference clock cycle (cclkx). the dev ice is reset by the internal power- on reset (por) circuitry during power-up. outputs enabled (active) vco_sel, fsel_a[0:1], fsel_b[0:1], fsel_c[0:1], fsel_fb[0:2] control the operating pll frequency range and input/output frequen cy ratios. see table 3 to table 6 and the applications information for supported frequency ranges and output to input frequency ratios. table 3. output divider bank a (n a ) vco_sel fsel_a1 fsel_a0 qa[0:3] 0 0 0 vco ? 8 0 0 1 vco ? 12 0 1 0 vco ? 16 0 1 1 vco ? 24 1 0 0 vco ? 4 1 0 1 vco ? 6 1 1 0 vco ? 8 1 1 1 vco ? 12 table 4. output divider bank b (n b ) vco_sel fsel_b1 fsel_b0 qb[0:3] 0 0 0 vco ? 8 0 0 1 vco ? 12 0 1 0 vco ? 16 0 1 1 vco ? 20 1 0 0 vco ? 4 1 0 1 vco ? 6 1 1 0 vco ? 8 1 1 1 vco ? 10 table 5. output divider bank c (n c ) vco_sel fsel_c1 fsel_c0 qc[0:3] 0 0 0 vco ? 4 0 0 1 vco ? 8 0 1 0 vco ? 12 0 1 1 vco ? 16 1 0 0 vco ? 2
MPC9772 revision 7 january 8, 2013 5 ?2013 integrated device technology, inc. MPC9772 data sheet 3.3v 1:12 lvcmos pll clock generator 1 0 1 vco ? 4 1 1 0 vco ? 6 1 1 1 vco ? 8 table 6. output divider pll feedback (m) vco_sel fsel_fb2 fsel_fb1 fsel_fb0 qfb 0 0 0 0 vco ? 8 0 0 0 1 vco ? 12 0 0 1 0 vco ? 16 0 0 1 1 vco ? 20 0 1 0 0 vco ? 16 0 1 0 1 vco ? 24 0 1 1 0 vco ? 32 0 1 1 1 vco ? 40 1 0 0 0 vco ? 4 1 0 0 1 vco ? 6 1 0 1 0 vco ? 8 1 0 1 1 vco ? 10 1 1 0 0 vco ? 8 1 1 0 1 vco ? 12 1 1 1 0 vco ? 16 1 1 1 1 vco ? 20 table 7. general specifications symbol characteristics min typ max unit condition v tt output termination voltage v cc ? 2 v mm esd protection (machine model) 200 v hbm esd protection (human body model) 2000 v lu latch-up immunity 200 ma c pd power dissipation capacitance 12 pf per output c in input capacitance 4.0 pf inputs table 8. absolute maximum ratings (1) 1. absolute maximum continuous ratings are those maximum values beyond which damage to t he device may occur. exposure to these conditions or conditions beyond thos e indicated may adversely affect device reli ability. functional operat ion at absolute-maxim um-rated conditions is not implied. symbol characteristics min max unit condition v cc supply voltage ?0.3 3.9 v v in dc input voltage ?0.3 v cc +0.3 v v out dc output voltage ?0.3 v cc +0.3 v i in dc input current ? 20 ma i out dc output current ? 50 ma t s storage temperature ?65 125 ? c table 5. output divider bank c (n c ) vco_sel fsel_c1 fsel_c0 qc[0:3]
MPC9772 revision 7 january 8, 2013 6 ?2013 integrated device technology, inc. MPC9772 data sheet 3.3v 1:12 lvcmos pll clock generator table 9. dc characteristics (v cc = 3.3 v 5%, t a = -40 to 85c) symbol characteristics min typ max unit condition v cc_pll pll supply voltage 3.0 v cc v lvcmos v ih input high voltage 2.0 v cc + 0.3 v lvcmos v il input low voltage 0.8 v lvcmos v oh output high voltage 2.4 v i oh = ?24 ma (1) 1. the MPC9772 is capable of driving 50 ? transmission lines on the inciden t edge. each output drives one 50 ? parallel terminated transmission line to a termination voltage of v tt . alternatively, the device drives up to two 50 ? series terminated transmission lines. v ol output low voltage 0.55 0.30 v v i ol = 24 ma i ol = 12 ma z out output impedance 14 ? 17 ? i in input current (2) 2. inputs have pull-down resistors affecting the input current. ? 200 ? a v in = v cc or gnd i cc_pll maximum pll supply current 3.0 5.0 ma v cc_pll pin i ccq maximum quiescent supply current 15 ma all v cc pins table 10. ac characteristics (v cc = 3.3 v 5%, t a = ?40 to +85c) (1) , (2) , continued on next page symbol characteristics min typ max unit condition t a = 0c to +70c t a = ?40c to +85c f ref input reference frequency ? 4 feedback ? 6 feedback ? 8 feedback ? 10 feedback ? 12 feedback ? 16 feedback ? 20 feedback ? 24 feedback ? 32 feedback ? 40 feedback input reference frequency in pll bypass mode (3) 50.0 33.3 25.0 20.0 16.6 12.5 10.0 8.33 6.25 5.00 120.0 80.0 60.0 48.0 40.0 30.0 24.0 20.0 15.0 12.0 250 115.00 76.67 57.50 46.00 38.33 28.75 23.00 19.16 14.37 11.50 250 mhz mhz mhz mhz mhz mhz mhz mhz mhz mhz mhz pll locked pll bypass f vco vco frequency range (4) 200 480 460 mhz f xtal crystal interface frequency range (4) 10 25 mhz f max output frequency ? 2 output ? 4 output ? 6 output ? 8 output ? 10 output ? 12 output ? 16 output ? 20 output ? 24 output 100.0 50.0 33.3 25.0 20.0 16.6 12.5 10.0 8.33 240.0 120.0 80.0 60.0 48.0 40.0 30.0 24.0 20.0 230.00 115.00 76.67 57.50 46.00 38.33 28.75 23.00 19.16 mhz mhz mhz mhz mhz mhz mhz mhz mhz pll locked f stop_clk serial interface clock frequency 20 mhz t pw,min input reference pulse width (5) 2.0 ns t r , t f cclkx input rise/fall time (6) 1.0 ns 0.8 to 2.0 v
MPC9772 revision 7 january 8, 2013 7 ?2013 integrated device technology, inc. MPC9772 data sheet 3.3v 1:12 lvcmos pll clock generator t ( ? ) propagation delay (static phase offset) (7) cclk to fb_in 6.25 mhz < f ref < 65.0 mhz 65.0 mhz < f ref < 125 mhz f ref =50 mhz and feedback= ? 8 ?3 ?4 ?166 +3 +4 +166 ? ? ps pll locked t sk(o) output-to-output skew (8) within qa outputs within qb outputs within qc outputs all outputs 100 100 100 250 ps ps ps ps dc output duty cycle (9) (t ? 2) ? 200 t ?? 2 (t ? 2) + 200 ps t r , t f output rise/fall time 0.1 1.0 ns 0.55 to 2.4 v t plz, hz output disable time 8 ns t pzl, lz output enable time 8 ns t jit(cc) cycle-to-cycle jitter (10) 150 200 ps t jit(per) period jitter (11) 150 ps t jit( ? ) i/o phase jitter rms (1 ? ) (12) ? 4 feedback ? 6 feedback ? 8 feedback ? 10 feedback ? 12 feedback ? 16 feedback ? 20 feedback ? 24 feedback ? 32 feedback ? 40 feedback 11 86 13 88 16 19 21 22 27 30 ps ps ps ps ps ps ps ps ps ps (vco=400 mhz) bw pll closed loop bandwidth (13) ? 4 feedback ? 6 feedback ? 8 feedback ? 10 feedback ? 12 feedback ? 16 feedback ? 20 feedback ? 24 feedback ? 32 feedback ? 40 feedback 1.20 ? 3.50 0.70 ? 2.50 0.50 ? 1.80 0.45 ? 1.20 0.30 ? 1.00 0.25 ? 0.70 0.20 ? 0.55 0.17 ? 0.40 0.12 ? 0.30 0.11 ? 0.28 mhz mhz mhz mhz mhz mhz mhz mhz mhz mhz t lock maximum pll lock time 10 ms 1. ac characteristics apply for par allel output termination of 50 ? to v tt . 2. in bypass mode, the MPC9772 divides the input reference clock. 3. the input reference frequency must match the vco lock range divided by the total feedback divider ratio: f ref = f vco ? (m t vco_sel). 4. the crystal frequency range must both meet the interface fr equency range and vco lock range divi ded by the feedback divider r atio: f xtal(min, max) = f vco(min, max) ? (m ? vco_sel) and 10 mhz ? f xtal ? 25 mhz. 5. calculation of reference duty cycle limits: dc ref,min = t pw,min ? f ref ? 100% and dc ref,max = 100% ? dc ref, min . 6. the MPC9772 will operate with input rise/fall times up to 3.0 ns, but the a.c. characteristics, specifically t ( ? ) , t pw,min , dc and f max can only be guaranteed if t r , t f are within the specified range. 7. static phase offset depends on the reference frequency. t ( ? ) [s] = t ( ? ) [ ? ] ? (f ref ? 360 ? ). 8. excluding qsync output. see application se ction for part-to-part skew calculation. 9. output duty cycle is dc = (0.5 ? 200 ps ? f out ) ? 100%. e.g. the dc range at f out = 100 mhz is 48% < dc < 52%. t = output period. 10. cycle jitter is valid for all outputs in the same divider configuration. see applications information section for more details. 11. period jitter is valid for all outputs in the same divider configuration. see applications information section for more details. 12. i/o jitter is valid for a vco frequency of 400 mhz. see applications information section for i/o jitter vs. vco frequency. 13. ?3 db point of pll transfer characteristics. table 10. ac characteristics (v cc = 3.3 v 5%, t a = ?40 to +85c) (1) , (2) , continued on next page symbol characteristics min typ max unit condition t a = 0c to +70c t a = ?40c to +85c
MPC9772 revision 7 january 8, 2013 8 ?2013 integrated device technology, inc. MPC9772 data sheet 3.3v 1:12 lvcmos pll clock generator applications information MPC9772 configurations configuring the MPC9772 amount s to properly configuring the internal dividers to produce the desired output frequencies. the output frequency can be represented by this formula: where f ref is the reference frequency of the selected input clock source (cclko, cclk1 or xtal interface), m is the pll feedback divider and n is a output divider. the pll feedback divider is configured by the fsel_fb[2:0] and the output dividers are individually configured for each output bank by the fsel_a[1:0], fsel_b[1:0] and fsel_c[1:0] inputs. the reference frequency f ref and the selection of the feedback-divider m is limited by the specified vco frequency range. f ref and m must be configured to match the vco frequency range of 200 to 480 mhz in order to achieve stable pll operation: f vco,min ? (f ref ? vco_sel ? m) ? f vco,max the pll post-divider vco_sel is either a divide-by-one or a divide-by-two and can be used to situate the vco into the specified frequency range. this divider is controlled by the vco_sel pin. vco_sel effectively extends the usable input frequency range while it has no effect on the output to reference frequency ratio. the output frequency for each bank can be derived from the vco frequency and output divider: f qa[0:3] = f vco ? (vco_sel ? n a ) f qb[0:3] = f vco ? (vco_sel ? n b ) f qc[0:3] = f vco ? (vco_sel ? n c ) ta b l e 11 shows the various pll feedback and output dividers and figure 3 and figure 4 display example configurations for the MPC9772: ? vco_sel ? m ? n f ref f out f out = f ref ? m ? n pll table 11. MPC9772 divider divider function vco_sel values m pll feedback fsel_fb[0:3] ? 1 4, 6, 8, 10, 12, 16 ? 2 8, 12, 16, 20, 24, 32, 40 n a bank a output divider fsel_a[0:1] ? 1 4, 6, 8, 12 ? 2 8, 12, 16, 24 n b bank b output divider fsel_b[0:1] ? 1 4, 6, 8, 10 ? 2 8, 12, 16, 20 n c bank c output divider fsel_c[0:1] ? 1 2, 4, 6, 8 ? 2 4, 8, 12, 16
MPC9772 revision 7 january 8, 2013 9 ?2013 integrated device technology, inc. MPC9772 data sheet 3.3v 1:12 lvcmos pll clock generator MPC9772 individual output disable (clock stop) circuitry the individual clock stop (output enable) control of the MPC9772 allows designers, under software control, to implement power management into the clock distribution design. a simple serial interface and a clock stop control logic provides a mechanism through which the MPC9772 clock outputs can be individually stopped in the logic ?0? state: the clock stop mechanism allows serial loading of a 12-bit serial input register. this register contains one programmable clock stop bit for 12 of the 14 output clocks. the qc0 and qfb outputs cannot be stopped (disabled) with the serial port. the user can program an output clock to stop (disable) by writing logic ?0? to the respective stop enable bit. likewise, the user may programmably enable an output clock by writing logic ?1? to the respective enable bit. the clock stop logic enables or disables clock outputs during the time when the output would be in normally in logic low state, eliminating the possibility of short or ?runt? clock pulses. the user can write to the serial input register through the stop_data input by supplying a logic ?0? start bit followed serially by 12 nrz disable/enable bits. the period of each stop_data bit equals the period of the free?running stop_clk signal. the stop_data serial transmission should be timed so the MPC9772 can sample each stop_data bit with the rising edge of the free?running stop_clk signal. (see figure 5 .) sync output description the MPC9772 has a system synch ronization pulse output qsync. in configurations with the output frequency relationships are not integer multiples of each other qsync provides a signal for system synchronization purposes. the MPC9772 monitors the relationship between the a bank and the b bank of outputs. the qsync output is asserted (logic low) one period in duration and one period prior to the coincident rising edges of the qa and qc outputs. the duration and the placement of the pulse is dependent qa and qc output frequencies: the qsync pulse width is equal to the period of the higher of the qa and qc output frequencies. figure 6 shows various waveforms for the qsync output. the qsync output is defined for all possible combinations of the bank a and bank c outputs. figure 3. example configuration figure 4. example configuration MPC9772 f ref = 33.3 mhz 33.3 mhz 100 mhz 33.3 mhz (feedback) 200 mhz cclk0 vco_sel fsel_a[1:0] fsel_b[1:0] fsel_c[1:0] fsel_fb[2:0] qa[3:0] qb[3:0] qc[3:0] qfb cclk1 cclk_sel fb_in 1 11 00 00 101 MPC9772 example configuration (feedback of qfb = 33.3 mhz, f vco =400 mhz, vco_sel= ? 1, m=12, n a =12, n b =4, n c =2). frequency range t a = 0c to +70c t a = ?40c to +85c input 16.6 ? 40 mhz 16.6 ? 38.33 mhz qa outputs 16.6 ? 40 mhz 16.6 ? 38.33 mhz qa outputs 50 ? 120 mhz 50 ? 115 mhz qc outputs 100 ? 240 mhz 100 ? 230 mhz MPC9772 f ref = 25 mhz 62.5 mhz 62.5 mhz 25 mhz (feedback) 125 mhz cclk0 vco_sel fsel_a[1:0] fsel_b[1:0] fsel_c[1:0] fsel_fb[2:0] qa[3:0] qb[3:0] qc[3:0] qfb cclk1 cclk_sel fb_in 1 00 00 00 011 MPC9772 example configuration (feedback of qfb = 25 mhz, f vco =250 mhz, vco_sel= ? 1, m=10, n a =4, n b =4, n c =2). frequency range t a = 0c to +70c t a = ?40c to +85c input 20 ? 48 mhz 20 ? 46 mhz qa outputs 50 ? 120 mhz 50 ? 115 mhz qa outputs 50 ? 120 mhz 50 ? 115 mhz qc outputs 100 ? 240 mhz 100 ? 230 mhz figure 5. clock stop circuit programming stop_clk stop_data start qa0 qa1 qa2 qa3 qb0 qb1 qb2 qb3 qc1 qc2 qc3 qsync
MPC9772 revision 7 january 8, 2013 10 ?2013 integrated device technology, inc. MPC9772 data sheet 3.3v 1:12 lvcmos pll clock generator figure 6. qsync timing diagram f vco 1:1 mode qa qc qsync 2:1 mode qc( ? 2) qa( ? 6) qsync 3:1 mode qa qc qsync qa( ? 4) qc( ? 6) qsync 3:2 mode qc( ? 2) qa( ? 8) qsync 4:1 mode qa( ? 6) qc( ? 8) qsync 4:3 mode qa( ? 12) qc( ? 2) qsync 6:1 mode
MPC9772 revision 7 january 8, 2013 11 ?2013 integrated device technology, inc. MPC9772 data sheet 3.3v 1:12 lvcmos pll clock generator power supply filtering the MPC9772 is a mixed analog/digital product. its analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. random noise on the v cc_pll power supply impacts the device characteristics, for instance i/o jitter. the MPC9772 provides separate power supplies for the output buffers (v cc ) and the phase-locked loop (v cc_pll ) of the device. the purpose of this design technique is to isol ate the high switching noise digital outputs from the relatively sensitive internal analog phase-locked loop. in a digita l system environm ent where it is more difficult to minimize noise on the power supplies a second level of isolation may be required. the simple but effective form of isolation is a power supply filter on the v cca_pll pin for the MPC9772. figure 7 illustrates a typical power supply filter scheme. the MPC9772 frequency and phase stability is most susceptible to noise with spectral content in the 100 khz to 20 mh z range. therefor e the filter should be designed to target this range. the key parameter that needs to be met in the final filter design is the dc voltage drop across the series filter resistor r f . from the data sheet the i cc_pll current (the current sourced through the v cc_pll pin) is typically 3 ma (5 ma maximum), assuming that a minimum of 3.0 v must be maintained on the v cc_pll pin. the resistor r f shown in figure 7 must have a resistance of 5-10 ? to meet the voltage drop criteria. figure 7. v cc_pll power supply filter the minimum values for r f and the filter capacitor c f are defined by the required filter characteristics: the rc filter should provide an attenuation greater than 40 db for noise whose spectral content is above 100 khz. in the example rc filter shown in figure 7 , the filter cut-off frequency is around 4.5 khz and the noise attenuatio n at 100 khz is better than 42 db. as the noise frequency crosses the series resonant point of an individual capacitor its overall impedance begins to look inductive and thus increases with increasing frequency. the parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the pll. although the MPC9772 has several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential pll) there still may be applications in which overall performance is being degraded due to system power supply noise. the power supply filter schemes discussed in this section should be adequate to eliminate power supply noise related problems in most designs. using the MPC9772 in zero-delay applications nested clock trees are typical applications for the MPC9772. designs using the MPC9772 as lvcmos pll fanout buffer with zero insertion delay will show significantly lower clock skew than clock distributions developed from cmos fanout buffers. the external feedback option of the MPC9772 clock driver allows for its use as a zero delay buffer. the pll aligns the feedback clock output edge with the clock input reference edge resulting a near zero delay through the device (the propagation delay through the device is virtually eliminated). the maximum insertion delay of the device in zero-delay applications is measured between the reference clock input and any output. this effective delay consists of the static phase offset, i/o jitter (phase or long-term jitter), feedback path delay and the output-to-output skew error relative to the feedback output. calculation of part-to-part skew the MPC9772 zero delay buffer supports applications where critical clock signal timing can be maintained across several devices. if the reference clock inputs of two or more MPC9772 are connected together, the maximum overall timing uncertainty from the common cclkx input to any output is: t sk(pp) = t ( ? ) + t sk(o) + t pd, line(fb) + t jit( ? ) ? cf this maximum timing uncertainty consist of 4 components: static phase offset, output skew, feedback board trace delay and i/o (phase) jitter: figure 8. MPC9772 maximum device-to-device skew due to the statistical nature of i/o jitter a rms value (1 ? ) is specified. i/o jitter numbers for other confidence factors v cc_pll v cc MPC9772 10 nf r f = 5?10 ? c f 33...100 nf r f v cc c f = 22 ? f t pd,line(fb) t jit( ? ) + t sk(o) ?t ( ? ) +t ( ? ) t jit( ? ) + t sk(o) t sk(pp) max. skew cclk common qfb device 1 any q device 1 qfb device2 any q device 2
MPC9772 revision 7 january 8, 2013 12 ?2013 integrated device technology, inc. MPC9772 data sheet 3.3v 1:12 lvcmos pll clock generator (cf) can be derived from table 12 . the feedback trace delay is determined by the board layout and can be used to fine-tune the effective delay through each device. due to the frequency dependence of the static phase offset and i/o jitter, using figure 9 to figure 11 to predict a maximum i/o jitter and the specified t ( ? ? parameter relative to the input reference frequency results in a precise timing performance analysis. in the following example calculation an i/o jitter confidence factor of 99.7% ( ? 3 ? ) is assumed, resulting in a worst case timing uncertainty from the common input reference clock to any output of ?455 ps to +455 ps relative to cclk (pll feedback = ? 8, reference frequency = 50 mhz, vco frequency = 400 mhz, i/o jitter = 13 ps rms max., static phase offset t ( ? ) = ? 166 ps): t sk(pp) = [-166ps...166ps] + [-250ps...250ps] + [(13ps @ ?3)...(13ps @ 3)] + t pd, line(fb) t sk(pp) = [-455ps...455ps] + t pd, line(fb) figure 9. MPC9772 i/o jitter figure 10. MPC9772 i/o jitter figure 11. MPC9772 i/o jitter driving transmission lines the MPC9772 clock driver was designed to drive high speed signals in a terminated transmission line environment. to provide the optimum flexib ility to the user the output drivers were designed to exhibit the lowest impedance possible. with an output impedance of less than 20 ? the drivers can drive either parallel or series terminated transmission lines. for more information on transmission lines the reader is referred to freescale semiconductor application note an1091. in most high performance clock networks point-to-point distributi on of signals is the method of choice. in a point-to-point scheme either series terminated or parallel terminated transmission lines can be used. the parallel technique terminates the signal at the end of the line with a 50 ? resistance to v cc ? 2. this technique draws a fairly high level of dc current and thus only a single terminated line can be driven by each output of the MPC9772 clock driv er. for the series terminated case however there is no dc current draw, thus the outputs can drive multiple series terminated lines. figure 12 illustrates an output driving a single series terminated line versus two series terminated lines in parallel. when taken to its extreme the fanout of the MPC9772 clock driver is effectively doubled due to its capability to drive multiple lines. table 12. confidence factor cf cf probability of clock edge within the distribution ? 1 ? 0.68268948 ? 2 ? 0.95449988 ? 3 ? 0.99730007 ? 4 ? 0.99993663 ? 5 ? 0.99999943 ? 6 ? 0.99999999 vco frequency [mhz] 200 250 300 350 400 450 480 160 140 120 100 80 60 40 20 0 fb= ? 32 fb= ? 16 fb= ? 8 fb= ? 4 max. i/o phase jitter versus frequency parameter: pll feedback divider fb t jit( ? ) [ps] rms vco frequency [mhz] 200 250 300 350 400 450 480 120 100 80 60 40 20 0 fb= ? 12 fb= ? 24 max. i/o phase jitter versus frequency parameter: pll feedback divider fb fb= ? 6 t jit( ? ) [ps] rms vco frequency [mhz] 200 250 300 350 400 450 480 140 120 100 80 60 40 20 0 fb= ? 20 fb= ? 10 fb= ? 40 max. i/o phase jitter versus frequency parameter: pll feedback divider fb t jit( ? ) [ps] rms
MPC9772 revision 7 january 8, 2013 13 ?2013 integrated device technology, inc. MPC9772 data sheet 3.3v 1:12 lvcmos pll clock generator figure 12. single versus dual transmission lines the waveform plots in figure 13 show the simulation results of an output driving a single line versus two lines. in both cases the drive capability of the MPC9772 output buffer is more than sufficient to drive 50 ? transmission lines on the incident edge. note from the delay measurements in the simulations a delta of only 43 ps exists between the two differently loaded outputs. this suggests the dual line driving need not be used exclusively to maintain the tight output-to-output skew of the MPC9772. the output waveform in figure 13 shows a step in the waveform, this step is caused by the impedance mismatch seen looking into the driver. the parallel combination of the 36 ? series resistor plus the output impedance does not match the parallel combination of the line impedances. the voltage wave launched down the two lines will equal: v l =v s (z 0 ? (r s +r 0 +z 0 )) z 0 =50 ?? || 50 ?? r s =36 ? || 36 ? r 0 =14 ?? v l = 3.0 (25 ? (18+17+25) =1.31 v at the load end the voltage will double, due to the near unity reflection coefficient, to 2.6 v. it will then increment towards the quiescent 3.0 v in steps separated by one round trip delay (in this case 4.0 ns). figure 13. single versus dual waveforms since this step is well above the threshold region it will not cause any false clock triggering, however designers may be uncomfortable with unwanted reflections on the line. to better match the impedances when driving multiple lines the situation in figure 14 should be used. in this case the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched. figure 14. optimized dual line termination figure 15. cclk MPC9772 ac test reference 14 ? in MPC9772 output buffer r s = 36 ? z o = 50 ? outa 14 ? in MPC9772 output buffer r s = 36 ? z o = 50 ? outb0 r s = 36 ? z o = 50 ? outb1 time (ns) voltage (v) 3.0 2.5 2.0 1.5 1.0 0.5 0 2 4 6 8 10 12 14 outb t d = 3.9386 outa t d = 3.8956 in 14 ? MPC9772 output buffer r s = 22 ? z o = 50 ? r s = 22 ? z o = 50 ? 14 ? + 22 ? || 22 ? = 50 ? || 50 ? 25 ? = 25 ? pulse generator z = 50 ? r t = 50 ? z o = 50 ? r t = 50 ? z o = 50 ? MPC9772 dut v tt v tt
MPC9772 revision 7 january 8, 2013 14 ?2013 integrated device technology, inc. MPC9772 data sheet 3.3v 1:12 lvcmos pll clock generator figure 16. output-to-output skew t sk(o) figure 17. propagation delay (t ( ? ) , static phase offset) test reference figure 18. output duty cycle (dc) the pin-to-pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device the time from the pll controlled edge to the non controlled edge, divided by the time between pll controlled edges, expressed as a percentage v cc v cc ? 2 gnd v cc v cc ? 2 gnd t sk(o) v cc v cc ? 2 gnd t p t 0 dc = t p /t 0 x 100% v cc v cc ? 2 gnd v cc v cc ? 2 gnd t ( ? ) cclkx fb_in t jit( ? ) = | t 0 -t 1 mean | cclkx fb_in the deviation in t 0 for a controlled edge with respect to a t 0 mean in a random sample of cycles figure 19. i/o jitter t n t jit(cc) = | t n -t n+1 | t n+1 t jit(per) = | t n -1 / f 0 | t 0 figure 20. cycle-to-cycle ji tter figure 21. period jitter the variation in cycle time of a si gnal between adjacent cycles, over a random sample of adjacent cycle pairs the deviation in cycle time of a signal with respect to the ideal period over a random sample of cycles t f t r v cc =3.3 v 2.4 0.55 figure 22. output transition time test reference
notes: 1. 2. 3. 4. 5. 6. 7. controlling dimensions: millimeter. dimensioning and tolerancing per ansi y14.5m, 1982. datum plane -h- is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. datums -l-, -m- and -n- to be determined at datum plane -h-. dimensions s and v to be determined at seating plane -t-. dimensions a and b do not include mold protrusion. allowable protrusion is 0.25 (0.010) per side. dimensions a and b do include mold mismatch and are determined at datum plane -h-. dimension d does not include dambar protrusion. dambar protrusion shall not cause the lead width to exceed 0.46 (0.018). minimum space between protrusion and adjacent lead or protrustion 0.07 (0.003). f section ab-ab rotated 90? clockwise s l-m m 0.13 (0.005) n s t plating base metal d j u s 0.05 (0.002) 0.25 (0.010) gage plane c2 c1 w k e z 1 view aa 2x r r1 1 13 14 26 27 39 40 52 4x 13 tips 4x n 0.20 (0.008) h l-m n 0.20 (0.008) t l-m b v b1 a s v1 a1 s1 -l- -n- -m- 3x view y view aa seating plane c 0.10 (0.004) t 4x 3 4x 2 -h- -t- dim a a1 b b1 c c1 c2 d e f g j k r1 s s1 u v v1 w z 1 3 2 min --- 0.05 1.30 0.20 0.45 0.22 0.07 0.08 0.09 0? 0? min --- 0.002 0.051 0.008 0.009 0.018 0.003 0.003 0.004 0? 0? max 1.70 0.20 1.50 0.40 0.35 0.75 0.20 0.20 0.16 7? --- max 0.067 0.008 0.059 0.016 0.030 0.014 0.008 0.008 0.006 7? --- millimeters 10.00 bsc 5.00 bsc 10.00 bsc 5.00 bsc 0.65 bsc 0.50 ref 12.00 bsc 6.00 bsc 12.00 bsc 6.00 bsc 0.20 ref 1.00 ref 12? ref 12? ref inches 0.394 bsc 0.197 bsc 0.394 bsc 0.197 bsc 0.026 bsc 0.020 ref 0.472 bsc 0.236 bsc 0.472 bsc 0.236 bsc 0.008 ref 0.039 ref 12? ref 12? ref ab ab view y c l -x- x=l, m, n g case 848d-03 issue d 52-lead lqfp package MPC9772 revision 7 january 8, 2013 15 ?2013 integrated device technology, inc. MPC9772 data sheet 3.3v 1:12 lvcmos pll clock generator
MPC9772 revision 7 january 8, 2013 16 ?2013 integrated device technology, inc. MPC9772 data sheet 3.3v 1:12 lvcmos pll clock generator revision history sheet rev table page description of change date 7 1 nrnd ? not recommend for new designs 1/8/13
disclaimer integrated device technology, inc. (idt) and its subsidiaries reserve the ri ght to modify the products and/or specif ications described herein at any time and at idt? s sole discretion. all information in this document, including descriptions of product features and performance, is s ubject to change without notice. performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when in stalled in customer products. the informa tion contained herein is provided without re presentation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of idt?s products for any partic ular purpose, an implied warranty of merc hantability, or non-infringement of the in tellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third parties. idt?s products are not intended for use in applications involving extreme environmenta l conditions or in life support systems o r similar devices where the failure or malfunction of an idt product can be reasonably expected to signifi- cantly affect the health or safety of users. anyone using an id t product in such a manner does so at their own risk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are registered tr ademarks of idt. other trademarks and service marks used he rein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright 2013. all rights reserved. 6024 silver creek valley road san jose, california 95138 sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt technical support netcom@idt.com +480-763-2056 we?ve got your timing solution MPC9772 data sheet 3.3v 1:12 lvcmos pll clock generator

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